Design and Evaluation of a Switch

Cache coherent non-uniform memory access (CC-NUMA) multiprocessors provide a scal-able design for shared memory but they continue to suuer from large remote memory access latencies due to comparatively slow memory technology and data transfer latencies in the in-terconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote memory access performance of CC-NUMA multiproces-sors. The main idea is to implement small fast caches in crossbar switches of the interconnect medium to capture and store shared data as they ow from the memory module to the requesting processor. This stored data acts as a cache for subsequent requests, thus reducing the need for remote memory accesses tremendously. The implementation of a cache in a crossbar switch needs to be eecient and robust, yet exible for changes in the caching protocol. The design and implementation details of a CAche Embedded Switch ARchitecture, CAESAR, using wormhole routing with virtual channels is presented. We explore the design space of switch caches by modeling CAESAR in a detailed execution driven simulator and analyzing the performance beneets. Our results show that the CAESAR switch cache is capable of improving the performance of CC-NUMA multiprocessors by up to 45% reduction in remote memory accesses for some applications. By serving remote read requests at various stages in the interconnect, we observe improvements in execution time as high as 20% for these applications. We conclude that switch caches provide a cost-eeective solution for designing high performance CC-NUMA multiprocessors.